? semiconductor components industries, llc, 2009 april, 2009 ? rev. 0 1 publication order number: nb6lq572/d nb6lq572 2.5v / 3.3v differential 4:1 mux w/input equalizer to 1:2 lvpecl clock/data fanout / translator multi ? level inputs w/ internal termination the nb6lq572 is a high performance differential 4:1 clock/data input multiplexer and a 1:2 lvpecl clock / data fanout buffer that operates up to 5 ghz / 6.5 gbps respectively with a 2.5 v or 3.3 v power supply. each inx/inx input pair incorporates a fixed equalizer receiver, which w hen placed in series with a clock / data path, will enhance the degraded signal transmitted across an fr4 backplane or cable interconnect. for applications that do not require equalization, consider the nb6l572, which is pin ? compatible to the nb6lq572. the differential clock / data inputs have internal 50 termination resistors and will accept differential lvpecl, cml, or lvds logic levels. the nb6lq572 incorporates a pair of select pins that will choose one of four differential inputs and will produce two identical lvpecl output copies of clock or data. as such, the nb6lq572 is ideal for sonet, gige, fiber channel, backplane and other clock/data distribution applications. the two differential lvpecl outputs will swing 750 mv when externally loaded and terminated with a 50 resistor to v cc ? 2 v and are optimized for low skew and minimal jitter. the nb6lq572 is offered in a low profile 5x5 mm 32 ? pin qfn pb ? free package. application notes, models, and support documentation are available at www.onsemi.com. the nb6lq572 is a member of the eclinps max ? family of high performance clock products. features ? input data rate > 6.5 gb/s typical ? data dependent jitter < 10 ps ? maximum input clock frequency > 5 ghz typical ? random clock jitter < 0.8ps rms ? fixed input equalization ? low skew 1:2 lvpecl outputs, < 15 ps max ? 4:1 multi ? level mux inputs, accepts lvpecl, cml lvds ? 150ps typical propagation delay ? 55ps typical rise and fall times ? differential lvpecl outputs, 800 mv peak ? to ? peak, typical ? operating range: v cc = 2.375 v to 3.6 v ? internal 50 input termination resistors ? v refac reference output ? qfn ? 32 package, 5mm x 5mm ? ? 40 c to +85 c ambient operating temperature ? these are pb ? free devices qfn32 mn suffix case 488am see detailed ordering and shipping information on page 9 of this data sheet. ordering information marking diagram http://onsemi.com 32 1 nb6l q572 awlyyww 1 a = assembly location wl = wafer lot yy = year ww = work week = pb ? free package (note: microdot may be in either location)
nb6lq572 http://onsemi.com 2 50 50 in3 vt3 in3 50 50 in2 vt2 in2 50 50 in1 vt1 in1 figure 1. simplified block diagram 50 50 in0 vt0 in0 eq0 eq1 eq2 eq3 0 1 2 3 sel0 sel1 lvpecl outputs 4:1 mux vrefac3 vrefac2 vrefac1 vrefac0 multilevel inputs lvpecl, lvds, cml q0 q0 q1 q1 figure 2. pinout: qfn ? 32 (top view) 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 910111213 16 15 14 32 31 30 29 28 25 26 27 in0 vt0 vrefac0 in0 in1 vt1 vrefac1 in1 gnd vcc q1 vcc nc sel1 vcc q1 gnd vcc q0 vcc sel0 nc vcc q0 vrefac3 vt3 in3 vrefac2 vt2 in2 in3 in2 exposed pad (ep) table 1. input select function table sel1* sel0* clock / data input selected 0 0 in0 input selected 0 1 in1 input selected 1 0 in2 input selected 1 1 in3 input selected *defaults high when left open.
nb6lq572 http://onsemi.com 3 table 2. pin description pin num- ber pin name i/o pin description 1, 4 5, 8 25, 28 29, 32 in0, in0 in1, in1 in2, in2 in3, in3 lvpecl, cml, lvds input noninverted, inverted, differential clock or data inputs 2, 6 26, 30 vt0, vt1 vt2, vt3 internal 100 center ? tapped termination pin for inx / inx 15 18 sel0 sel1 lvttl/lvcmos input input select pins, default high when left open through a 94 k pullup resistor. input logic threshold is v cc / 2. see select function, table 1. 14, 19 nc ? no connect 10, 13, 16 17, 20, 23 v cc ? positive supply voltage. 11, 12 21, 22 q0 , q0 q1 , q1 lvpecl output non ? inverted, inverted differential outputs. 9, 24 gnd negative supply voltage 3 7 27 31 vrefac0 vrefac1 vrefac2 vrefac3 ? output voltage reference for capacitor ? coupled inputs ? ep ? the exposed pad (ep) on the qfn ? 32 package bottom is thermally connected to the die for improved heat transfer out of package. the exposed pad must be attached to a heat ? sinking conduit. the pad is electrically connected to the die, and must be electrically connected to gnd. 1. in the differential configuration when the input termination pins (vt0, vt1, vt2, vt3) are connected to a common termination voltage or left open, and if no signal is applied on inx/inx input, then the device will be susceptible to self ? oscillation. 2. all v cc and gnd pins must be externally connected to a power supply for proper operation.
nb6lq572 http://onsemi.com 4 table 3. attributes characteristics value esd protection human body model machine model > 2 kv > 200 v r pu ? selx input pull ? up resistor 94 k moisture sensitivity (note 3) qfn ? 32 level 1 flammability rating oxygen index: 28 to 34 ul 94 v ? 0 @ 0.125 in transistor count 221 meets or exceeds jedec spec eia/jesd78 ic latchup test 3. for additional information, see application note and8003/d. table 4. maximum ratings symbol parameter condition 1 condition 2 rating unit v cc positive power supply gnd = 0 v ? 0.5 to +4.0 v v in positive input voltage gnd = 0 v ? 0.5 to v cc +0.5 v v inpp differential input voltage |in ? in | 1.89 v i out lvpecl output current continuous surge 50 100 ma i in input current through rt (50 resistor) 40 ma i vrefac v refac sink or source current 1.5 ma t a operating temperature range ? 40 to +85 c t stg storage temperature range ? 65 to +150 c ja thermal resistance (junction ? to ? ambient) (note 4) 0 lfpm 500 lfpm qfn ? 32 qfn ? 32 31 27 c/w jc thermal resistance (junction ? to ? case) (note 4) qfn ? 32 12 c/w t sol wave solder 20 sec 265 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 4. jedec standard multilayer board ? 2s2p (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
nb6lq572 http://onsemi.com 5 table 5. dc characteristics positive lvpecl output v cc = 2.375 v to 3.6 v, gnd = 0 v, t a = ? 40 c to +85 c (note 5) symbol characteristic min typ max unit power supply v cc power supply voltage v cc = 2.5 v v cc = 3.3 v 2.375 3.0 2.5 3.3 2.625 3.6 v i cc power supply current for v cc (inputs and outputs open) 75 110 ma lvpecl outputs v oh output high voltage (note 6) v cc = 2.5 v v cc = 3.3 v v cc ? 1145 1355 2155 v cc ? 900 1600 2400 v cc ? 800 1700 2500 mv v ol output low voltage (note 6) v cc = 2.5 v v cc = 3.3 v v cc ? 2000 500 1300 v cc ? 1700 800 1600 v cc ? 1500 1000 1800 mv differential clock inputs driven single ? ended (note 7) (figures 5 and 6) v ih single ? ended input high voltage v th + 100 v cc mv v il single ? ended input low voltage gnd v th ? 100 mv v th input threshold reference voltage range (note 8) 1100 v cc ? 100 mv v ise single ? ended input voltage (v ih ? v il ) 200 1200 mv vrefac v refac output reference voltage (100 a load) v cc ? 1300 v cc ? 1100 v cc ? 900 mv differential inputs driven differentially (note 9) (figures 7 and 8) v ihd differential input high voltage (in x , in x ) 1200 v cc mv v ild differential input low voltage (in x , in x ) 0 v ihd ? 100 mv v id differential input voltage (in x , in x ) (v ihd ? v ild ) 100 1200 mv v cmr input common mode range (differential configuration) (note 10) (figure 9) 1150 v cc ? 50 mv i ih input high current in x /in x (vt x /vt x open) ? 150 150 a i il input low current in x /in x (vt x /vt x open) ? 150 150 a control input (selx pin) v ih input high voltage for control pin 2.0 v cc v v il input low voltage for control pin gnd 0.8 v i ih input high current ? 150 150 a i il input low current ? 150 150 a termination resistors r tin internal input termination resistor (measured from inx to vtx) 45 50 55 note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. input and output parameters vary 1:1 with v cc . 6. lvpecl outputs loaded with 50 to v cc ? 2 v for proper operation. 7. vth, v ih , v il,, and v ise parameters must be complied with simultaneously. 8. vth is applied to the complementary input when operating in single ? ended mode. 9. v ihd , v ild, v id and v cmr parameters must be complied with simultaneously. 10. v cmr min varies 1:1 with gnd, v cmr max varies 1:1 with v cc . the v cmr range is referenced to the most positive side of the differential input signal.
nb6lq572 http://onsemi.com 6 table 6. ac characteristics v cc = 2.375 v to 3.6 v, gnd = 0 v, t a = ? 40 c to +85 c (note 11) symbol characteristic min typ max unit f max maximum input clock frequency v out 450 mv 5 6 ghz f datamax maximum operating data rate nrz, (prbs23) 6.5 8 gbps f sel maximum toggle frequency, selx 4 10 mhz v outpp output voltage amplitude (@ v inppmin ) f in 5 ghz (note 11) (figures 3 and 10) 450 800 mv t plh , t phl propagation delay to differential outputs measured at differential crosspoint inx/inx to qx/qx @1 ghz @ 50 mhz seln to qx 100 175 5 250 10 ps ns t pd te m p c o differential propagation delay temperature coefficient 100 fs/ c tskew output ? output skew (within device) (note 13) device ? device skew (t pdmax ? t pdmin ) 0 30 15 100 ps t dc output clock duty cycle (reference duty cycle = 50%) f in = 1 ghz 45 50 55 % n phase noise, f in = 1 ghz 10 khz 100 khz 1 mhz 10 mhz 20 mhz ? 134 ? 136 ? 149 ? 150 ? 150 dbc t n integrated phase jitter (figure 1) fin = 1ghz, 12 khz ? 20 mhz offset (rms) 35 fs t jitter random clock jitter, rj(rms), (note 14) deterministic jitter, dj (note 15) 0.2 0.8 10 ps crosstalk induced jitter (adjacent channel) (note 16) 0.7 psrms v inpp input voltage swing (differential configuration) (note 17) 100 1200 mv t r, , t f output rise/fall times @ 1 ghz; (20% ? 80%), qx, qx 25 50 75 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 11. measured using a v inppmin source, 50% duty cycle clock source. all output loading with external 50 to v cc ? 2 v. input edge rates 40 ps (20% ? 80%). 12. output voltage swing is a single ? ended measurement operating in differential mode. 13. skew is measured between outputs under identical transitions and conditions. duty cycle skew is defined only for differential operation when the delays are measured from cross ? point of the inputs to the cross ? point of the outputs. 14. additive rms jitter with 50% duty cycle clock signal. 15. additive peak ? to ? peak data dependent jitter with input nrz data at prbs23. 16. crosstalk is measured at the output while applying two similar clock frequencies that are asynchronous with respect to each other at the inputs. 17. input voltage swing is a single ? ended measurement operating in differential mode. 900 850 800 750 700 650 600 550 500 0 f in , clock input frequency (ghz) figure 3. clock output voltage amplitude (v outpp ) vs. input frequency (f in ) at ambient temperature (typical) 8.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 output voltage amplitude (mv) q amp (mv)
nb6lq572 http://onsemi.com 7 figure 4. input structure figure 5. differential input driven single ? ended figure 6. v th diagram figure 7. differential inputs driven differentially figure 8. differential inputs driven differentially figure 9. vcmr diagram figure 10. ac reference measurement v ihd v ild v id = |v ihd(in) ? v ild(in) | in in in v th in in in in in q q t plh t phl v inpp = v ih (in) ? v il (in) v outpp = v oh (q) ? v ol (q) 50 50 inx vtx inx v cc v ee v thmin v thmax vth in v ihmax v ilmax v ih v th v il v ihmin v ilmin v cc v ee v cmmin v cmmax v cmr in in v ihdmax v ildmax v id = v ihd ? v ild v ihdtyp v ildtyp v ihdmin v ildmin v th v ih v il figure 11. selx to qx timing diagram tpd tpd v cc / 2 v cc / 2 selx q q v cc
nb6lq572 http://onsemi.com 8 v cc lvpecl driver in 50 z o = 50 z o = 50 50 in nb6lq572 v cc v cc cml driver in 50 z o = 50 z o = 50 50 in nb6lq572 v cc v t = v cc figure 12. lvpecl interface figure 13. lvds interface v t = v cc ? 2.0 v figure 14. standard 50 load cml interface v cc lvds driver in 50 z o = 50 z o = 50 50 in nb6lq572 v cc v t = open gnd gnd gnd gnd gnd gnd v cc differential driver in 50 z o = 50 z o = 50 50 in nb6lq572 v cc v t = v refac * figure 15. capacitor ? coupled differential interface (v t connected to external v refac ) gnd gnd *v refac bypassed to ground with a 0.01 f capacitor. clkx clkx figure 16. typical termination for output driver and device evaluation (see application note and8020/d ? termination of ecl logic devices) q d driver device receiver device 50 50 q d v tt v tt = v cc ? 2.0 v z o = 50 z o = 50
nb6lq572 http://onsemi.com 9 figure 17. typical nb6lq572 equalizer application and interconnect with prbs23 pattern at 6.5 gbps fr4 ? 12 inch backplane driver dj1 dj2 dj3 nb6lq572 equalizer vtx inx q q inx device ordering information device package shipping ? NB6LQ572MNG qfn ? 32 (pb ? free) 74 units / rail nb6lq572mnr4g qfn ? 32 (pb ? free) 1000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
nb6lq572 http://onsemi.com 10 package dimensions qfn32 5*5*1 0.5 p case 488am ? 01 issue o seating 32 x k 0.15 c (a3) a a1 d2 b 1 9 16 17 32 2 x 2 x e2 32 x 8 24 32 x l 32 x bottom view exposed pad top view side view d a b e 0.15 c pin one location 0.10 c 0.08 c c 25 e a 0.10 b c 0.05 c notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm terminal 4. coplanarity applies to the exposed pad as well as the terminals. plane dim min nom max millimeters a 0.800 0.900 1.000 a1 0.000 0.025 0.050 a3 0.200 ref b 0.180 0.250 0.300 d 5.00 bsc d2 2.950 3.100 3.250 e 5.00 bsc e2 e 0.500 bsc k 0.200 ??? ??? l 0.300 0.400 0.500 2.950 3.100 3.250 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.50 pitch 3.20 0.28 3.20 32 x 28 x 0.63 32 x 5.30 5.30 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. sc illc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems in tended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hol d scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising ou t of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding th e design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resa le in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 nb6lq572/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca l sales representative
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